Flip Flops and Latches

In: Other Topics

Submitted By jackjack22522
Words 714
Pages 3
Flip-Flops & Latches
Digital Electronics

Flip-Flops & Latches
This presentation will
• Review sequential logic and the flip-flop. • Introduce the D flip-flop and provide an excitation table and a sample timing analysis. • Introduce the J/K flip-flop and provide an excitation table and a sample timing analysis. • Review flip-flop clock parameters. • Introduce the transparent D-latch. • Discuss flip-flop asynchronous inputs.
2

Sequential Logic & The Flip-Flop

Inputs

. .

Combinational Logic Gates

. .

Outputs

Clock

Memory Elements (Flip-Flops)

3

D Flip-Flop: Excitation Table

D
D Q

CLK
 

Q
0 1

Q
1 0

0 1

CLK

Q
 : Rising Edge of Clock

4

D Flip-Flop: Example Timing
Q=D=1 Q=D=0 Q=D=0
No Change

Q=D=1

Q=D=1
No Change

Q=D=0

Q=D=0
No Change

Q D CLK

5

J/K Flip-Flop: Excitation Table

J
J CLK K Q

K
0 1 0 1

CLK
   

Q
Q0
No Change Clear Set Toggle

0

Q

0 1 1

0 1
Q0

 : Rising Edge of Clock
Q : Complementof Q

6

J/K Flip-Flop: Example Timing
SET TOGGLE TOGGLE CLEAR NO CHANGE SET NO CHANGE

Q J K CLK

7

Clock Edges
Positive Edge Transition

1 0

1 0

Negative Edge Transition
8

POS & NEG Edge Triggered D
Positive Edge Trigger
D
D Q

CLK
 

Q
0 1

Q
1 0

0 1

CLK

Q
 : Rising Edge of Clock

Negative Edge Trigger
D
D Q

CLK



Q
0
1

Q
1
0
9

0
1

CLK

Q
 : Falling Edge of Clock

POS & NEG Edge Triggered J/K
Positive Edge Trigger
J
J CLK K Q

K 0 1 0 1

CLK
   

Q
Q0

0 0 1 1

0 1
Q0

Q

 : Rising Edge of Clock

Negative Edge Trigger
J
J CLK K Q

K 0 1 0

CLK
  

Q
Q0

0 0 1

0 1
Q0
10

Q

1

1



 : Rising Edge of Clock

Flip-Flop Timing
Data Input (D,J, or K) 1 0

tS
Setup Time
Positive Edge Clock 1 0

tH…...

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